module rt72_fifo_ctrl (
dclk,
reset_n,

rd_sram0,
rd_sram1,
rd_sram2,
rd_sram3,
rd_line_no,

sd_div12,
data_rvs,
port_4n,
port_4n_add2,

lb1_out,
lb2_out,
lb3_out,
lb4_out,

//output for write
din0, din1, din2, din3,
din4, din5, din6, din7,
din8, din9, din10, din11,
din12, din13, din14, din15,

wen0, wen1, wen2, wen3,		
wen4, wen5, wen6, wen7,		
wen8, wen9, wen10, wen11,		
wen12, wen13, wen14, wen15,		

clka0, clka1, clka2, clka3,	
clka4, clka5, clka6, clka7,	
clka8, clka9,	clka10,	clka11,	
clka12, clka13, clka14, clka15,	

addra0, addra1, addra2, addra3,
addra4, addra5, addra6, addra7,
addra8, addra9, addra10, addra11,
addra12, addra13, addra14, addra15,

//output for read
cen0,	cen1, cen2, cen3,		
cen4, cen5,	cen6,	cen7,		
cen8,	cen9,	cen10, cen11,		
cen12, cen13,	cen14, cen15,		

clkb0, clkb1, clkb2, clkb3,	
clkb4, clkb5,	clkb6, clkb7,	
clkb8, clkb9,	clkb10,	clkb11,	
clkb12,	clkb13, clkb14,	clkb15,	

addrb0, addrb1, addrb2, addrb3,
addrb4, addrb5, addrb6, addrb7,
addrb8, addrb9, addrb10, addrb11,
addrb12, addrb13, addrb14, addrb15,

rd_line_no

);

input dclk;
input reset_n;

input fifo_ctrl_en;
input [1:0] rd_line_no;

input sd_div12,
input data_rvs,
input port_4n,
input port_4n_add2,

input [29:0] sram0_lb1_out, sram0_lb2_out, sram0_lb3_out, sram0_lb4_out;
input [29:0] sram1_lb1_out, sram1_lb2_out, sram1_lb3_out, sram1_lb4_out;
input [29:0] sram2_lb1_out, sram2_lb2_out, sram2_lb3_out, sram2_lb4_out;
input [29:0] sram3_lb1_out, sram3_lb2_out, sram3_lb3_out, sram3_lb4_out;

//output for write
output [29:0] din0, din1, din2, din3;
output [29:0] din4, din5, din6, din7;
output [29:0] din8, din9, din10, din11;
output [29:0] din12, din13, din14, din15;

output wen0, wen1, wen2, wen3;
output wen4, wen5, wen6, wen7;		
output wen8, wen9, wen10, wen11;		
output wen12, wen13, wen14, wen15;		

output [3:0] addra0, addra1, addra2, addra3;   //FIFO depth=16
output [3:0] addra4, addra5, addra6, addra7;
output [3:0] addra8, addra9, addra10, addra11;
output [3:0] addra12, addra13, addra14, addra15;

//output for read
output cen0, cen1, cen2, cen3;
output cen4, cen5, cen6, cen7;		
output cen8, cen9, cen10, cen11;		
output cen12, cen13, cen14, cen15;		
 
output clkb0, clkb1, clkb2, clkb3;	
output clkb4, clkb5, clkb6, clkb7;	
output clkb8, clkb9, clkb10, clkb11;	
output clkb12, clkb13, clkb14,	clkb15;	

output [3:0] addrb0, addrb1, addrb2, addrb3;    //FIFO depth=16
output [3:0] addrb4, addrb5, addrb6, addrb7;
output [3:0] addrb8, addrb9, addrb10, addrb11;
output [3:0] addrb12, addrb13, addrb14, addrb15;

reg rd_sram0_d1, rd_sram1_d1, rd_sram2_d1, rd_sram3_d1;
reg rd_sram0_d2, rd_sram1_d2, rd_sram2_d2, rd_sram3_d2;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
    rd_sram0_d1 <= 10'd0; 
    rd_sram1_d1 <= 10'd0; 
    rd_sram2_d1 <= 10'd0; 
    rd_sram3_d1 <= 10'd0; 
    rd_sram0_d2 <= 10'd0; 
    rd_sram1_d2 <= 10'd0;  
    rd_sram2_d2 <= 10'd0; 
    rd_sram3_d2 <= 10'd0;    
 end else begin
    rd_sram0_d1 <= rd_sram0; 
    rd_sram1_d1 <= rd_sram1; 
    rd_sram2_d1 <= rd_sram2; 
    rd_sram3_d1 <= rd_sram3; 
    rd_sram0_d2 <= rd_sram0_d1; 
    rd_sram1_d2 <= rd_sram1_d1;  
    rd_sram2_d2 <= rd_sram2_d1; 
    rd_sram3_d2 <= rd_sram3_d1; end
end

reg [29:0] sram_lb1_data, sram_lb2_data, sram_lb3_data, sram_lb4_data;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  sram_lb1_data <= 30'd0; 
  sram_lb2_data <= 30'd0; 
  sram_lb3_data <= 30'd0; 
  sram_lb4_data <= 30'd0;     
 end else if (rd_sram0_d2) begin
     sram_lb1_data <= sram0_lb1_out; 
     sram_lb2_data <= sram0_lb2_out; 
     sram_lb3_data <= sram0_lb3_out; 
     sram_lb4_data <= sram0_lb4_out; end
     else if (rd_sram1_d2) begin
          sram_lb1_data <= sram1_lb1_out; 
          sram_lb2_data <= sram1_lb2_out; 
          sram_lb3_data <= sram1_lb3_out; 
          sram_lb4_data <= sram1_lb4_out; end
          else if (rd_sram2_d2) begin
               sram_lb1_data <= sram2_lb1_out; 
               sram_lb2_data <= sram2_lb2_out; 
               sram_lb3_data <= sram2_lb3_out; 
               sram_lb4_data <= sram2_lb4_out; end
               else if (rd_sram3_d2) begin
                    sram_lb1_data <= sram3_lb1_out; 
                    sram_lb2_data <= sram3_lb2_out; 
                    sram_lb3_data <= sram3_lb3_out; 
                    sram_lb4_data <= sram3_lb4_out; end          
end


//reg [29:0] sram0_lb1_data, sram0_lb2_data, sram0_lb3_data, sram0_lb4_data;
//always @(posedge dclk or negedge reset_n)
//begin
// if (!reset_n)
// begin
//  sram0_lb1_data <= 30'd0; 
//  sram0_lb2_data <= 30'd0; 
//  sram0_lb3_data <= 30'd0; 
//  sram0_lb4_data <= 30'd0;     
// end else if (rd_sram0_d2) begin
//     sram0_lb1_data <= sram0_lb1_out; 
//     sram0_lb2_data <= sram0_lb2_out; 
//     sram0_lb3_data <= sram0_lb3_out; 
//     sram0_lb4_data <= sram0_lb4_out; end
//          else begin
//          sram0_lb1_data <= 30'd0; 
//          sram0_lb2_data <= 30'd0; 
//          sram0_lb3_data <= 30'd0; 
//          sram0_lb4_data <= 30'd0; end
//end


//reg [29:0] sram1_lb1_data, sram1_lb2_data, sram1_lb3_data, sram1_lb4_data;
//always @(posedge dclk or negedge reset_n)
//begin
// if (!reset_n)
// begin
//  sram1_lb1_data <= 30'd0; 
//  sram1_lb2_data <= 30'd0; 
//  sram1_lb3_data <= 30'd0; 
//  sram1_lb4_data <= 30'd0;     
// end else if (rd_sram1_d2) begin
//     sram1_lb1_data <= sram1_lb1_out; 
//     sram1_lb2_data <= sram1_lb2_out; 
//     sram1_lb3_data <= sram1_lb3_out; 
//     sram1_lb4_data <= sram1_lb4_out; end
//          else begin
//          sram1_lb1_data <= 30'd0; 
//          sram1_lb2_data <= 30'd0; 
//          sram1_lb3_data <= 30'd0; 
//          sram1_lb4_data <= 30'd0; end
//end


//reg [29:0] sram2_lb1_data, sram2_lb2_data, sram2_lb3_data, sram2_lb4_data;
//always @(posedge dclk or negedge reset_n)
//begin
// if (!reset_n)
// begin
//  sram2_lb1_data <= 30'd0; 
//  sram2_lb2_data <= 30'd0; 
//  sram2_lb3_data <= 30'd0; 
//  sram2_lb4_data <= 30'd0;     
// end else if (rd_sram2_d2) begin
//     sram2_lb1_data <= sram2_lb1_out; 
//     sram2_lb2_data <= sram2_lb2_out; 
//     sram2_lb3_data <= sram2_lb3_out; 
//     sram2_lb4_data <= sram2_lb4_out; end
//          else begin
//          sram2_lb1_data <= 30'd0; 
//          sram2_lb2_data <= 30'd0; 
//          sram2_lb3_data <= 30'd0; 
//          sram2_lb4_data <= 30'd0; end
//end


//reg [29:0] sram3_lb1_data, sram3_lb2_data, sram3_lb3_data, sram3_lb4_data;
//always @(posedge dclk or negedge reset_n)
//begin
// if (!reset_n)
// begin
//  sram3_lb1_data <= 30'd0; 
//  sram3_lb2_data <= 30'd0; 
//  sram3_lb3_data <= 30'd0; 
//  sram3_lb4_data <= 30'd0;     
// end else if (rd_sram3_d2) begin
//     sram3_lb1_data <= sram3_lb1_out; 
//     sram3_lb2_data <= sram3_lb2_out; 
//     sram3_lb3_data <= sram3_lb3_out; 
//     sram3_lb4_data <= sram3_lb4_out; end
//          else begin
//          sram3_lb1_data <= 30'd0; 
//          sram3_lb2_data <= 30'd0; 
//          sram3_lb3_data <= 30'd0; 
//          sram3_lb4_data <= 30'd0; end
//end


wire rd_sram0_d2_pe = rd_sram0_d2 & (~rd_sram0_d2);


//address change cnt
reg [2:0] addr_change_cnt_stop;                         // only for 4n case
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  addr_change_cnt_stop <= 3'd0;  
 end else if (port_4n) 
     addr_change_cnt_stop <= {port_num[4:2]}-3'd1;
          else 
          addr_change_cnt_stop <= 4'd0;
end

reg [2:0] addr_change_cnt;                              // only for 4n case                      
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  addr_change_cnt <= 3'd0; 
 end else if (rd_sram0_d2_pe)
     addr_change_cnt <= 3'd0; 
          else if (addr_change_cnt == addr_change_cnt_stop)
          addr_change_cnt <= 3'd0;
               else
               addr_change_cnt <= addr_change_cnt + 3'd1;
end

reg [2:0] addr_change_cnt_d1;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
   addr_change_cnt_d1 <= 3'd0; 
 else
   addr_change_cnt_d1 <= addr_change_cnt;
 end


 
 
 
 
// address cnt
reg [3:0] addr_cnt;                                      //FIFO depth=16
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  addr_cnt <= 4'd0; 
 end else if (rd_sram0_d2_pe)
     addr_cnt <= 4'd0;
          else if (addr_change_cnt == addr_change_cnt_stop) 
          addr_cnt <= addr_change + 4'd1;
               else
               addr_cnt <= addr_cnt;
end

reg [3:0] addr_cnt_d1;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
   addr_cnt_d1 <= 4'd0; 
 else
   addr_cnt_d1 <= addr_cnt;
 end






//cycle cnt
wire sd_div12 = (sd_ch_num[1:0] == 2'd0);         //SD_CH/4 =\=0, special case-1026ch

reg [3:0] cycle_cnt_stop;                             //count LB cycle ( 4n case=4, (4n+2 case)=port_num )
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
  cycle_cnt_stop <= 4'd0; 
 end else if (port_4n)
     cycle_cnt_stop <= 4'd3;
          else if (port_4n_add2)
          cycle_cnt_stop <= port_num[3:0]-4'd1;
               else 
               cycle_cnt_stop <= 4'd0; 
end

reg [3:0] cycle_cnt;
always @(posedge dclk or negedge reset_n)   //4n-nml
begin
 if (!reset_n)
 begin
  cycle_cnt <= 4'd0; 
 end else if (rd_sram0_d2_pe)
     cycle_cnt <= 4'd0;
          //else if ((cycle_cnt == cycle_cnt_stop) & (addr_change_cnt == addr_change_cnt_stop))
          //cycle_cnt <= 4'd0;
               else if (addr_change_cnt == addr_change_cnt_stop)
               cycle_cnt[1:0] <= cycle_cnt[1:0] + 2'd1;
                    else
                    cycle_cnt <= cycle_cnt;
end

end else if (rd_sram0_d2_pe)                 //4n-rvs, sd_div12=1
     cycle_cnt <= 4'd1;
     else if (addr_change_cnt == addr_change_cnt_stop)
          cycle_cnt[1:0] <= cycle_cnt[1:0] - 2'd1;
          else
          cycle_cnt <= cycle_cnt;

 end else if (rd_sram0_d2_pe)                 //4n-rvs, sd_div12=0
     cycle_cnt <= 4'd3;
     else if (addr_change_cnt == addr_change_cnt_stop)
          cycle_cnt[1:0] <= cycle_cnt[1:0] - 2'd1;
          else
          cycle_cnt <= cycle_cnt;       

end else if (rd_sram0_d2_pe)                 //(4n+2)-nml 
     cycle_cnt <= 4'd0;
     else if (cycle_cnt == cycle_cnt_stop)
          cycle_cnt <= 4'd0;
          else
          cycle_cnt <= cycle_cnt + 4'd1;          
          
          
  end else if (rd_sram0_d2_pe)                 //(4n+2)-rvs, sd_div12=0
     cycle_cnt <= cycle_cnt_stop;
     else if (cycle_cnt == 4'd0)
          cycle_cnt <= 4'd5;
          else
          cycle_cnt <= cycle_cnt - 4'd1;        
          
          
  end else if (rd_sram0_d2_pe)                 //(4n+2)-rvs, sd_div12=1
     cycle_cnt <= 4'd2;
     else if (cycle_cnt == 4'd0)
          cycle_cnt <= 4'd5;
          else
          cycle_cnt <= cycle_cnt - 4'd1;   






          
          
          




reg [3:0] cycle_cnt_d1;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
   cycle_cnt_d1 <= 4'd0; 
 else
   cycle_cnt_d1 <= cycle_cnt;
 end







// FIFO ctrl - write in FIFO

//4n case
//wen
wire wen0 = (addr_change_cnt_d1 == 4'd0);
wire wen1 = (addr_change_cnt_d1 == 4'd0);
wire wen2 = (addr_change_cnt_d1 == 4'd0);
wire wen3 = (addr_change_cnt_d1 == 4'd0); 
wire wen0_p1 = (addr_change_cnt == 4'd0);
wire wen1_p1 = (addr_change_cnt == 4'd0);
wire wen2_p1 = (addr_change_cnt == 4'd0);
wire wen3_p1 = (addr_change_cnt == 4'd0);
                            
wire wen4 = (addr_change_cnt_d1 == 4'd1);
wire wen5 = (addr_change_cnt_d1 == 4'd1);
wire wen6 = (addr_change_cnt_d1 == 4'd1); 
wire wen7 = (addr_change_cnt_d1 == 4'd1); 
wire wen4_p1 = (addr_change_cnt == 4'd1);
wire wen5_p1 = (addr_change_cnt == 4'd1);
wire wen6_p1 = (addr_change_cnt == 4'd1); 
wire wen7_p1 = (addr_change_cnt == 4'd1); 

wire wen8 = (addr_change_cnt_d1 == 4'd2);
wire wen9 = (addr_change_cnt_d1 == 4'd2);
wire wen10 = (addr_change_cnt_d1 == 4'd2); 
wire wen11 = (addr_change_cnt_d1 == 4'd2);
wire wen8_p1 = (addr_change_cnt == 4'd2);
wire wen9_p1 = (addr_change_cnt == 4'd2);
wire wen10_p1 = (addr_change_cnt == 4'd2); 
wire wen11_p1 = (addr_change_cnt == 4'd2);

wire wen12 = (addr_change_cnt_d1 == 4'd3);
wire wen13 = (addr_change_cnt_d1 == 4'd3);
wire wen14 = (addr_change_cnt_d1 == 4'd3);
wire wen15 = (addr_change_cnt_d1 == 4'd3); 
wire wen12_p1 = (addr_change_cnt == 4'd3);
wire wen13_p1 = (addr_change_cnt == 4'd3);
wire wen14_p1 = (addr_change_cnt == 4'd3);
wire wen15_p1 = (addr_change_cnt == 4'd3);


//addra
wire [3:0] addra0 = addr_cnt_d1;
wire [3:0] addra1 = addr_cnt_d1;
wire [3:0] addra2 = addr_cnt_d1;
wire [3:0] addra3 = addr_cnt_d1;
//wire [3:0] addra0_p1 = addr_cnt;
//wire [3:0] addra1_p1 = addr_cnt;
//wire [3:0] addra2_p1 = addr_cnt;
//wire [3:0] addra3_p1 = addr_cnt;

wire [3:0] addra4 = addr_cnt_d1;
wire [3:0] addra5 = addr_cnt_d1;
wire [3:0] addra6 = addr_cnt_d1;
wire [3:0] addra7 = addr_cnt_d1;
//wire [3:0] addra4_p1 = addr_cnt;
//wire [3:0] addra5_p1 = addr_cnt;
//wire [3:0] addra6_p1 = addr_cnt;
//wire [3:0] addra7_p1 = addr_cnt;

wire [3:0] addra8 = addr_cnt_d1;
wire [3:0] addra9 = addr_cnt_d1;
wire [3:0] addra10 = addr_cnt_d1;
wire [3:0] addra11 = addr_cnt_d1;
//wire [3:0] addra8_p1 = addr_cnt;
//wire [3:0] addra9_p1 = addr_cnt;
//wire [3:0] addra10_p1 = addr_cnt;
//wire [3:0] addra11_p1 = addr_cnt;

wire [3:0] addra12 = addr_cnt_d1;
wire [3:0] addra13 = addr_cnt_d1;
wire [3:0] addra14 = addr_cnt_d1;
wire [3:0] addra15 = addr_cnt_d1;
//wire [3:0] addra12_p1 = addr_cnt;
//wire [3:0] addra13_p1 = addr_cnt;
//wire [3:0] addra14_p1 = addr_cnt;
//wire [3:0] addra15_p1 = addr_cnt;


//din0~3
reg [29:0] din0;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din0 <= 30'd0;
 else if (wen0_p1 & (cycle_cnt == 4'd0))
      din0 <= sram_lb1_data; 
      else if (wen0_p1 & (cycle_cnt == 4'd1))
           din0 <= sram_lb2_data;
           else if (wen0_p1 & (cycle_cnt == 4'd2))
                din0 <= sram_lb3_data;
                else if (wen0_p1 & (cycle_cnt == 4'd3))
                     din0 <= sram_lb4_data;
                     else
                     din0 <= 30'd0;
end
 
reg [29:0] din1;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din1 <= 30'd0;
 else if (wen1_p1 & (cycle_cnt == 4'd0))
      din1 <= sram_lb4_data;
       else if (wen1_p1 & (cycle_cnt == 4'd1))
           din1 <= sram_lb3_data;
           else if (wen1_p1 & (cycle_cnt == 4'd2))
                din1 <= sram_lb2_data;
                else if (wen1_p1 & (cycle_cnt == 4'd3))
                     din1 <= sram_lb1_data;
                     else
                     din1 <= 30'd0;
end
 
reg [29:0] din2;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din2 <= 30'd0;
 else if (wen2_p1 & (cycle_cnt == 4'd0))
      din2 <= sram_lb3_data;
      else if (wen2_p1 & (cycle_cnt == 4'd1))
          din2 <= sram_lb4_data;
          else if (wen2_p1 & (cycle_cnt == 4'd2))
               din2 <= sram_lb1_data;
               else if (wen2_p1 & (cycle_cnt == 4'd3))
                    din2 <= sram_lb2_data;
                    else
                    din2 <= 30'd0;      
end
 
reg [29:0] din3;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din3 <= 30'd0;
 else if (wen3_p1 & (cycle_cnt == 4'd0))
      din3 <= sram_lb2_data;
      else if (wen3_p1 & (cycle_cnt == 4'd1))
          din3 <= sram_lb1_data;
          else if (wen3_p1 & (cycle_cnt == 4'd2))
               din3 <= sram_lb4_data;
               else if (wen3_p1 & (cycle_cnt == 4'd3))
                    din3 <= sram_lb3_data;   
                    else
                    din3 <= 30'd0;      
end
 
 
 
 //din4~7
reg [29:0] din4;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din4 <= 30'd0;
 else if (wen4_p1 & (cycle_cnt == 4'd0))
      din4 <= sram_lb1_data;
      else if (wen4_p1 & (cycle_cnt == 4'd1))
           din4 <= sram_lb2_data;
           else if (wen4_p1 & (cycle_cnt == 4'd2))
                din4 <= sram_lb3_data;
                else if (wen4_p1 & (cycle_cnt == 4'd3))
                     din4 <= sram_lb4_data;
                     else
                     din4 <= 30'd0;
end
 
reg [29:0] din5;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din5 <= 30'd0;
 else if (wen5_p1 & (cycle_cnt == 4'd0))
      din5 <= sram_lb4_data;
      else if (wen5_p1 & (cycle_cnt == 4'd1))
          din5 <= sram_lb3_data;
          else if (wen5_p1 & (cycle_cnt == 4'd2))
               din5 <= sram_lb2_data;
               else if (wen5_p1 & (cycle_cnt == 4'd3))
                    din5 <= sram_lb1_data;
                    else
                    din5 <= 30'd0;                    
 end
 
 reg [29:0] din6;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din6 <= 30'd0;
 else if (wen6_p1 & (cycle_cnt == 4'd0))
      din6 <= sram_lb3_data;
      else if (wen6_p1 & (cycle_cnt == 4'd1))
          din6 <= sram_lb4_data;
          else if (wen6_p1 & (cycle_cnt == 4'd2))
               din6 <= sram_lb1_data;
               else if (wen6_p1 & (cycle_cnt == 4'd3))
                    din6 <= sram_lb2_data;   
                    else
                    din6 <= 30'd0;
 end
 
reg [29:0] din7;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din7 <= 30'd0;
 else if (wen7_p1 & (cycle_cnt == 4'd0))
      din7 <= sram_lb2_data;
       else if (wen7_p1 & (cycle_cnt == 4'd1))
           din7 <= sram_lb1_data;
           else if (wen7_p1 & (cycle_cnt == 4'd2))
                din7 <= sram_lb4_data;
                else if (wen7_p1 & (cycle_cnt == 4'd3))
                     din7 <= sram_lb3_data;      
                     else
                     din7 <= 30'd0;
 end
 
 
 
//din8~11
reg [29:0] din8;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din8 <= 30'd0;
 else if (wen8_p1 & (cycle_cnt == 4'd0))
      din8 <= sram_lb1_data;
      else if (wen8_p1 & (cycle_cnt == 4'd1))
           din8 <= sram_lb2_data;
           else if (wen8_p1 & (cycle_cnt == 4'd2))
                din8 <= sram_lb3_data;
                else if (wen8_p1 & (cycle_cnt == 4'd3))
                     din8 <= sram_lb4_data;
                     else
                     din8 <= 30'd0;
 end
 
 reg [29:0] din9;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din9 <= 30'd0;
 else if (wen9_p1 & (cycle_cnt == 4'd0))
      din9 <= sram_lb4_data;
      else if (wen9_p1 & (cycle_cnt == 4'd1))
          din9 <= sram_lb3_data;
          else if (wen9_p1 & (cycle_cnt == 4'd2))
               din9 <= sram_lb2_data;
               else if (wen9_p1 & (cycle_cnt == 4'd3))
                    din9 <= sram_lb1_data;
                    else
                    din9 <= 30'd0;      
 end
 
reg [29:0] din10;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din10 <= 30'd0;
 else if (wen10_p1 & (cycle_cnt == 4'd0))
      din10 <= sram_lb3_data;
       else if (wen10_p1 & (cycle_cnt == 4'd1))
           din10 <= sram_lb4_data;
           else if (wen10_p1 & (cycle_cnt == 4'd2))
                din10 <= sram_lb1_data;
                else if (wen10_p1 & (cycle_cnt == 4'd3))
                     din10 <= sram_lb2_data;     
                     else
                     din10 <= 30'd0;
end
 
reg [29:0] din11;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din11 <= 30'd0;
 else if (wen11_p1 & (cycle_cnt == 4'd0))
      din11 <= sram_lb2_data;
       else if (wen11_p1 & (cycle_cnt == 4'd1))
           din11 <= sram_lb1_data;
           else if (wen11_p1 & (cycle_cnt == 4'd2))
                din11 <= sram_lb4_data;
                else if (wen11_p1 & (cycle_cnt == 4'd3))
                     din11 <= sram_lb3_data;      
                     else
                     din11 <= 30'd0;
 end
 
  
 //din12~15
reg [29:0] din12;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din12 <= 30'd0;
 else if (wen12_p1 & (cycle_cnt == 4'd0))
      din12 <= sram_lb1_data;
      else if (wen12_p1 & (cycle_cnt == 4'd1))
           din12 <= sram_lb2_data;
           else if (wen12_p1 & (cycle_cnt == 4'd2))
                din12 <= sram_lb3_data;
                else if (wen12_p1 & (cycle_cnt == 4'd3))
                     din12 <= sram_lb4_data;           
                     else
                     din12 <= 30'd0;
 end
 
 reg [29:0] din13;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din13 <= 30'd0;
 else if (wen13_p1 & (cycle_cnt == 4'd0))
      din13 <= sram_lb4_data;
      else if (wen13_p1 & (cycle_cnt == 4'd1))
          din13 <= sram_lb3_data;
          else if (wen13_p1 & (cycle_cnt == 4'd2))
               din13 <= sram_lb2_data;
               else if (wen13_p1 & (cycle_cnt == 4'd3))
                    din13 <= sram_lb1_data;
                    else
                    din13 <= 30'd0;      
 end
 
reg [29:0] din14;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din14 <= 30'd0;
 else if (wen14_p1 & (cycle_cnt == 4'd0))
      din14 <= sram_lb3_data; 
      else if (wen14_p1 & (cycle_cnt == 4'd1))
          din14 <= sram_lb4_data;
          else if (wen14_p1 & (cycle_cnt == 4'd2))
               din14 <= sram_lb1_data;
               else if (wen14_p1 & (cycle_cnt == 4'd3))
                    din14 <= sram_lb2_data;  
                    else
                    din14 <= 30'd0;
 end
 
reg [29:0] din15;
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n) 
  din15 <= 30'd0;
 else if (wen15_p1 & (cycle_cnt == 4'd0))
      din15 <= sram_lb2_data;
      else if (wen15_p1 & (cycle_cnt == 4'd1))
          din15 <= sram_lb1_data;
          else if (wen15_p1 & (cycle_cnt == 4'd2))
               din15 <= sram_lb4_data;
               else if (wen15_p1 & (cycle_cnt == 4'd3))
                    din15 <= sram_lb3_data;     
                    else
                    din15 <= 30'd0;
 end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 



































































